The present invention relates to parameter extraction for circuit simulation of a semiconductor integrated circuit device including, for example, a plurality of MOSFETs (metal oxide semiconductor field effect transistors). In the specification, "MOSFET" is a general term for insulated gate field-effect transistors.
There are large scale integrated circuit devices including MOSFETs such as microprocessors. As a system for extracting parameters to be used for circuit simulation of a large scale integrated circuit device, a HICE (Hierarchical Circuit Extraction) system is known.
The HICE system is described in Proc. IEEE CICC (Custom Integrated Circuits Conference), May 1987, pp. 133-136, for example.
A semiconductor integrated circuit device is typically developed in accordance with procedures shown in FIG. 1.
In logic design procedure 10, it is determined what gate functions should be possessed by function blocks to be used and how those function blocks should be arranged.
In circuit design procedure 20, the circuit configuration of each function block is determined.
In layout pattern design procedure 30, the layout of a plurality of patterns for implementing, on a semiconductor wafer, the circuit configuration determined in circuit design procedure 20 is determined.
In delay library preparation procedure 40, the parameters for circuit simulation are extracted to prepare netlist or circuit descriptions by using layout information designed in the layout pattern design procedure 30 (410). Then, circuit simulation is executed to derive circuit delay data (420), and the circuit delay data are entered in a delay library together with pattern data, the netlist and the others (430).
FIG. 2 is a top view showing a part of a layout pattern of a semiconductor integrated circuit device. Layout patterns of two MOSFETs Q1 and Q2 are shown in FIG. 2. With reference to FIG. 2, the MOSFET Q1 has a linear gate SG laid out rectilinearly (i.e., having a rectilinear gate pattern) on an effective area (an area in which active elements should be formed such as a doped area having impurities introduced therein, which is referred to herein as a diffusion layer), whereas the MOSFET Q2 has a bent gate BG so laid out to be bent (i.e., having a bent gate pattern) on a diffusion layer DB.
In a conventional parameter extraction system, parameter extraction for the bent gate BG of the MOSFET Q2 was conducted in the same way as the parameter extraction for the linear gate SG of the MOSFET Q1. That is to say, the effective channel width W.sub.eff was derived as the total length of the gate pattern measured along the center lines of the bent gate BG as shown in FIG. 2 and represented as the sum W.sub.a +W.sub.b +W.sub.c (W.sub.eff =W.sub.a +W.sub.b +W.sub.c). In this method, however, the width effectively functioning as a channel in bends A and B having low current control capability was derived in the same way as the channel width in the linear gate SG. Therefore, the current control capability of the MOSFET Q2 derived by using the above described circuit simulation using W.sub.eff often produced an error of, say, approximately 5% with respect to the current control capability of the MOSFET Q2 of a semiconductor integrated circuit device actually manufactured.
Herein, the "current control capability" of a MOSFET is a value proportional to the value of a drain current let flow when predetermined voltages are applied to the drain and gate of the MOSFET.